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» An optimal architecture for a DDC
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CASES
2006
ACM
16 years 5 days ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
ASAP
2009
IEEE
157views Hardware» more  ASAP 2009»
16 years 3 months ago
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing
The advent of the mobile age has heavily changed the requirements of today’s communication devices. Data transmission over interference-prone wireless channels requires addition...
Andreas Genser, Christian Bachmann, Christian Steg...
ICC
2007
IEEE
107views Communications» more  ICC 2007»
16 years 15 days ago
The SILO Architecture for Services Integration, controL, and Optimization for the Future Internet
— We propose a new internetworking architecture that represents a departure from current philosophy and practice, as a contribution to the ongoing debate regarding the future Int...
Rudra Dutta, George N. Rouskas, Ilia Baldine, Arno...
CASES
2003
ACM
15 years 11 months ago
Architectural optimizations for low-power, real-time speech recognition
The proliferation of computing technology to low power domains such as hand–held devices has lead to increased interest in portable interface technologies, with particular inter...
Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 11 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha