3120 search results - page 78 / 624 » An optimal architecture for a DDC |
174
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CASES
2005
ACM
15 years 8 months ago
2005
ACM
Digital Signal Processing (DSP) is becoming increasingly widespread in portable devices. Due to harsh constraints on power, latency, and throughput in embedded environments, devel...
162
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SAC
2010
ACM
16 years 1 months ago
2010
ACM
In this paper, we discuss several facets of optimization in cloud computing, the corresponding challenges and propose an architecture for addressing those challenges. We consider ...
144
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ISQED
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
154
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ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
168
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CODES
2007
IEEE
16 years 15 days ago
2007
IEEE
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...