3120 search results - page 74 / 624 » An optimal architecture for a DDC |
187
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DAC
2004
ACM
15 years 10 months ago
2004
ACM
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
148
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ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
Low energy and small switch area usage are two of the important design objectives in FPGA global routing architecture design. This paper presents an improved MCF model based CAD ï...
140
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
With technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The Energyoptima...
133
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JCP
2007
15 years 6 months ago
2007
— Presented in this paper is a joint algorithm optimization and architecture design framework for analysis of repetitive regularities. Two closely coupled algorithm optimization ...
120
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TCAD
2002
15 years 5 months ago
2002
This paper proposes split shared-bus architecture to reduce the energy dissipation for global data exchange among a set of interconnected modules. The bus splitting problem for mi...