Sciweavers

3120 search results - page 547 / 624
» An optimal architecture for a DDC
Sort
View
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
16 years 16 days ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
DSN
2007
IEEE
16 years 16 days ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
ICC
2007
IEEE
168views Communications» more  ICC 2007»
16 years 15 days ago
Energy and QoS Aware Packet Forwarding in Wireless Sensor Networks
— We consider energy efficient packet forwarding with quality-of-service (QoS) guarantee for wireless sensor networks (WSNs). In most existing wireless network protocols, route ...
Rong Yu, Yan Zhang, Zhi Sun, Shunliang Mei
ICRA
2007
IEEE
160views Robotics» more  ICRA 2007»
16 years 15 days ago
OOPS for Motion Planning: An Online, Open-source, Programming System
— The success of sampling-based motion planners has resulted in a plethora of methods for improving planning components, such as sampling and connection strategies, local planner...
Erion Plaku, Kostas E. Bekris, Lydia E. Kavraki
IJCNN
2007
IEEE
16 years 15 days ago
Parallel Learning of Large Fuzzy Cognitive Maps
— Fuzzy Cognitive Maps (FCMs) are a class of discrete-time Artificial Neural Networks that are used to model dynamic systems. A recently introduced supervised learning method, wh...
Wojciech Stach, Lukasz A. Kurgan, Witold Pedrycz