Sciweavers

3120 search results - page 533 / 624
» An optimal architecture for a DDC
Sort
View
VLSID
2002
IEEE
123views VLSI» more  VLSID 2002»
16 years 6 months ago
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...
Victor Delaluz, Mahmut T. Kandemir, Narayanan Vija...
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
16 years 6 months ago
Evaluating Run-Time Techniques for Leakage Power Reduction
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishn...
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
16 years 6 months ago
Efficient Macromodeling for On-Chip Interconnects
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
Qinwei Xu, Pinaki Mazumder
VLSID
2002
IEEE
87views VLSI» more  VLSID 2002»
16 years 6 months ago
Simultaneous Circuit Transformation and Routing
In this paper, we propose a new methodology to integrate circuit transformation into routing. More specifically, this paper shows an approach for performing routing and wire recon...
Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahi...
HPCA
2008
IEEE
16 years 6 months ago
Power-Efficient DRAM Speculation
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti,...