3120 search results - page 532 / 624 » An optimal architecture for a DDC |
170
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VLSID
2007
IEEE
16 years 6 months ago
2007
IEEE
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
166
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
In the streaming video processing domain, the only way to meet strict performance and quality requirements and yet to provide the area- and power-wise optimal platform is to apply...
174
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
120
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VLSID
2003
IEEE
16 years 6 months ago
2003
IEEE
This paper quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module i...
161
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VLSID
2003
IEEE
16 years 6 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...