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» An optimal architecture for a DDC
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DAC
2008
ACM
16 years 7 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2008
ACM
16 years 7 months ago
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array fo
: Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRA...
Jing Li, Charles Augustine, Sayeef S. Salahuddin, ...
DAC
2008
ACM
16 years 7 months ago
Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems
Embedded systems with heterogeneous processors extend the energy/timing trade-off flexibility and provide the opportunity to fine tune resource utilization for particular applicat...
Michel Goraczko, Jie Liu, Dimitrios Lymberopoulos,...
DAC
2007
ACM
16 years 7 months ago
Chip Multi-Processor Generator
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
DAC
2007
ACM
16 years 7 months ago
Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design
Off-chip decoupling capacitor (decap) allocation is a demanding task during package and chip codesign. Existing approaches can not handle large numbers of I/O counts and large num...
Hao Yu, Chunta Chu, Lei He