Sciweavers

3120 search results - page 509 / 624
» An optimal architecture for a DDC
Sort
View
VLDB
2002
ACM
143views Database» more  VLDB 2002»
15 years 6 months ago
SQL Memory Management in Oracle9i
Complex database queries require the use of memory-intensive operators like sort and hashjoin. Those operators need memory, also referred to as SQL memory, to process their input ...
Benoît Dageville, Mohamed Zaït
PPOPP
2009
ACM
16 years 6 months ago
Mapping parallelism to multi-cores: a machine learning based approach
The efficient mapping of program parallelism to multi-core processors is highly dependent on the underlying architecture. This paper proposes a portable and automatic compiler-bas...
Zheng Wang, Michael F. P. O'Boyle
HPCA
2002
IEEE
16 years 6 months ago
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach
Power dissipation has become one of the most critical factors for the continued development of both high-end and low-end computer systems. The successful design and evaluation of ...
Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary J...
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
16 years 1 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
LCTRTS
2007
Springer
16 years 14 days ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...