3120 search results - page 506 / 624 » An optimal architecture for a DDC |
145
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IPPS
2010
IEEE
15 years 4 months ago
2010
IEEE
In this paper we present the venture of porting two different algorithms for solving the two-dimensional advection PDE on the CBE platform, an in-place and an outof-place one, and ...
177
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IPPS
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract--The growing complexity in computer system hierarchies due to the increase in the number of cores per processor, levels of cache (some of them shared) and the number of pr...
155
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
153
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
Recently, intellectual property protection (IPP) techniques attracted a great deal of attention from semiconductor, system integration and software companies. A number of watermar...
166
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
This paper presents a novel technique, called input space adaptive software synthesis, for the energy and performance optimization of embedded software. The proposed technique is ...