3120 search results - page 501 / 624 » An optimal architecture for a DDC |
193
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ARITH
2005
IEEE
15 years 12 months ago
2005
IEEE
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
156
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DATE
2005
IEEE
15 years 12 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
183
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DSN
2005
IEEE
15 years 12 months ago
2005
IEEE
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
189
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ICDE
2005
IEEE
15 years 12 months ago
2005
IEEE
Current federated systems deploy cost-based query optimization mechanisms; i.e., the optimizer selects a global query plan with the lowest cost to execute. Thus, cost functions in...
201
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ISLPED
2005
ACM
15 years 12 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...