3120 search results - page 497 / 624 » An optimal architecture for a DDC |
174
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EDOC
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—A simple and effective composition of software services into higher-level composite services is still a very challenging task. Especially in enterprise environments, Qua...
158
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IEEEPACT
2009
IEEE
16 years 1 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
150
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EUROPAR
2009
Springer
16 years 28 days ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
154
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ISAAC
2009
Springer
16 years 27 days ago
2009
Springer
Abstract. In a multicore transactional memory (TM) system, concurrent execution threads interact and interfere with each other through shared memory. The less interference a progra...
200
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MOBICOM
2009
ACM
16 years 26 days ago
2009
ACM
In cognitive radio networks (CRNs), spectrum sensing is key to opportunistic spectrum access while preventing any unacceptable interference to primary users’ communications. Alt...