3120 search results - page 494 / 624 » An optimal architecture for a DDC |
147
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WWW
2005
ACM
16 years 7 months ago
2005
ACM
In a mobile environment where mobile applications suffer from the limitation and variation of system resources availability, it is desirable for the applications to adapt their be...
156
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KDD
2006
ACM
16 years 6 months ago
2006
ACM
In this work we focus on the problem of frequent itemset mining on large, out-of-core data sets. After presenting a characterization of existing out-of-core frequent itemset minin...
155
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
182
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
229
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HPCA
2003
IEEE
16 years 6 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...