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» An optimal architecture for a DDC
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CF
2010
ACM
15 years 12 months ago
ERBIUM: a deterministic, concurrent intermediate representation for portable and scalable performance
Tuning applications for multi-core systems involve subtle concepts and target-dependent optimizations. New languages are being designed to express concurrency and locality without...
Cupertino Miranda, Philippe Dumont, Albert Cohen, ...
ICRA
2002
IEEE
105views Robotics» more  ICRA 2002»
15 years 11 months ago
Learning Behavioral Parameterization using Spatio-Temporal Case-Based Reasoning
This paper presents an approach to learning an optimal behavioral parameterization in the framework of a Case-Based Reasoning methodology for autonomous navigation tasks. It is ba...
Maxim Likhachev, Michael Kaess, Ronald C. Arkin
VLSID
2008
IEEE
166views VLSI» more  VLSID 2008»
16 years 7 months ago
Exploring the Processor and ISA Design for Wireless Sensor Network Applications
Power consumption, physical size, and architecture design of sensor node processors have been the focus of sensor network research in the architecture community. What lies at the ...
Shashidhar Mysore, Banit Agrawal, Frederic T. Chon...
HICSS
2003
IEEE
148views Biometrics» more  HICSS 2003»
16 years 5 days ago
Managing Multimedia Traffic in IP Integrated over Differentiated Services: SIP dynamic signaling inter-working
The current IETF standardization work has highlighted the feasibility of providing the users with a QoS network architecture in the framework of Integrated Services over Different...
Stefano Giordano, M. Mancino, A. Martucci, Saverio...
ET
2002
115views more  ET 2002»
15 years 6 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki