3120 search results - page 356 / 624 » An optimal architecture for a DDC |
174
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
171
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INFOCOM
2009
IEEE
16 years 1 months ago
2009
IEEE
—This paper studies the problem of allocating network capacity through periodic auctions. Motivated primarily by a service overlay architecture, we impose the following condition...
207
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FPGA
2007
ACM
16 years 1 months ago
2007
ACM
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because of its high degree of flexibility, short development time, and potentially high ...
194
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APCSAC
2005
IEEE
16 years 15 days ago
2005
IEEE
Abstract. Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for ...
201
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ICDE
2005
IEEE
16 years 15 days ago
2005
IEEE
¡ Several systems have recently been proposed for the evaluation of XPath expressions. However, none of these systems have demonstrated both scalability with large document sizes ...