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CGO
2007
IEEE
16 years 1 months ago
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
Amir Hormati, Nathan Clark, Scott A. Mahlke
FPGA
2007
ACM
106views FPGA» more  FPGA 2007»
16 years 1 months ago
A synthesizable datapath-oriented embedded FPGA fabric
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...
Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai ...
NOSSDAV
2004
Springer
16 years 7 days ago
Low latency and cheat-proof event ordering for peer-to-peer games
We are developing a distributed architecture for massivelymultiplayer games. In this paper, we focus on designing a low-latency event ordering protocol, called NEO, for this archi...
Chris GauthierDickey, Daniel Zappala, Virginia Mar...
IPPS
2003
IEEE
16 years 4 days ago
The CoGenT Project: Co-Generating Compilers and Simulators for Dynamically Compiled Languages
To understand the performance of modern Java systems one must observe execution in the context of specific architectures. It is also important that we make these observations usi...
J. Eliot B. Moss, Charles C. Weems, Timothy Richar...
WS
2003
ACM
16 years 3 days ago
On securely enabling intermediary-based services and performance enhancements for wireless mobile users
Intermediary-based services and performance optimizations are increasingly being considered, by network service providers, with a view towards offering value-added services and i...
Sneha Kumar Kasera, Semyon Mizikovsky, Ganapathy S...