3120 search results - page 351 / 624 » An optimal architecture for a DDC |
161
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SC
2004
ACM
16 years 9 days ago
2004
ACM
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...
162
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SAMOS
2004
Springer
16 years 6 days ago
2004
Springer
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
177
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CGO
2003
IEEE
16 years 5 days ago
2003
IEEE
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
174
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CF
2010
ACM
15 years 12 months ago
2010
ACM
Over the past decade, the trajectory to the petascale has been built on increased complexity and scale of the underlying parallel architectures. Meanwhile, software developers hav...
187
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IEEEPACT
1999
IEEE
15 years 11 months ago
1999
IEEE
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...