3120 search results - page 347 / 624 » An optimal architecture for a DDC |
211
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ISCA
2012
IEEE
13 years 9 months ago
2012
IEEE
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
176
Voted
VLSID
2005
IEEE
16 years 7 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
182
Voted
EUROPAR
2009
Springer
16 years 1 months ago
2009
Springer
Stencil based computation on structured grids is a common kernel to broad scientific applications. The order of stencils increases with the required precision, and it is a challeng...
205
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ISCA
2008
IEEE
16 years 1 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
189
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IESS
2007
Springer
16 years 1 months ago
2007
Springer
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspeciļ¬c architectures...