3120 search results - page 340 / 624 » An optimal architecture for a DDC |
181
click to vote
GLOBECOM
2006
IEEE
16 years 27 days ago
2006
IEEE
— Implementing a multi-tone (MT) architecture for high-speed backplane electrical links is difficult given the tight power and complexity constraints in this application. This pa...
185
click to vote
GECCO
2005
Springer
16 years 11 days ago
2005
Springer
As high-speed networks have proliferated across the globe, their topologies have become sparser due to the increased capacity of communication media and cost considerations. Relia...
205
click to vote
GECCO
2010
Springer
15 years 11 months ago
2010
Springer
We report the formulation and implementation of a genetic algorithm to address multi-objective optimisation of solar gain to buildings with the goal of minimising energy consumpti...
255
click to vote
ICCD
2008
IEEE
16 years 3 months ago
2008
IEEE
— Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance op...
193
click to vote
VLSID
2008
IEEE
16 years 1 months ago
2008
IEEE
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...