3120 search results - page 327 / 624 » An optimal architecture for a DDC |
153
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RECONFIG
2008
IEEE
16 years 1 months ago
2008
IEEE
This paper presents an embedded FPGA–based architecture to compute navigation trajectories along a harmonic potential. The goals and obstacles may be changed during computation....
174
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FPL
2004
Springer
16 years 6 days ago
2004
Springer
—This paper presents a methodology and a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology and...
198
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ATS
2002
IEEE
15 years 11 months ago
2002
IEEE
Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper, we survey recent advances in test planning that addre...
252
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
As the d esig n-m anu factu ring interface becom es increasing ly com plicated with IC technolog y scaling , the correspond ing process variability poses g reat challeng es for na...
134
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...