3120 search results - page 317 / 624 » An optimal architecture for a DDC |
198
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FPL
2007
Springer
15 years 10 months ago
2007
Springer
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
183
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CODES
2004
IEEE
15 years 10 months ago
2004
IEEE
Prior work on TLB power optimization considered circuit and architectural techniques. A recent software-based technique for data TLBs has considered the possibility of storing the...
164
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DAS
2006
Springer
15 years 10 months ago
2006
Springer
Traditional approaches to combining classifiers attempt to improve classification accuracy at the cost of increased processing. They may be viewed as providing an accuracy-speed tr...
177
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FDTC
2006
Springer
15 years 10 months ago
2006
Springer
Traditional hardware error detection methods based on linear codes make assumptions about the typical or expected errors and faults and concentrate the detection power towards the ...
183
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FPL
2006
Springer
15 years 10 months ago
2006
Springer
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...