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» An optimal architecture for a DDC
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IPPS
1998
IEEE
15 years 11 months ago
Memory Hierarchy Management for Iterative Graph Structures
The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications...
Ibraheem Al-Furaih, Sanjay Ranka
VLDB
1999
ACM
148views Database» more  VLDB 1999»
15 years 11 months ago
Loading a Cache with Query Results
Data intensive applications today usually run in either a clientserver or a middleware environment. In either case, they must efficiently handle both database queries, which proc...
Laura M. Haas, Donald Kossmann, Ioana Ursu
ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
15 years 11 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
ICLP
1993
Springer
15 years 11 months ago
A Minimal Extension of the WAM for clp(FD)
nt an abstract instruction set for a constraint solver over finite domains, which can be smoothly integrated in the WAM architecture. It is based on the use of a single primitive...
Daniel Diaz, Philippe Codognet
ASPDAC
2007
ACM
93views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Flow-Through-Queue based Power Management for Gigabit Ethernet Controller
- This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient Gigabit Ethernet controller. Key characteristics of suc...
Hwisung Jung, Andy Hwang, Massoud Pedram