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» An optimal architecture for a DDC
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HPCA
1996
IEEE
15 years 11 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
ICPP
1996
IEEE
15 years 11 months ago
On the Scalability of 2-D Wavelet Transform Algorithms on Fine-grained Parallel Machines
: We study the scalability of 2-D discrete wavelet transform algorithms on fine-grained parallel architectures. The principal operation in the 2-D DWT is the filtering operation us...
Jamshed N. Patel, Ashfaq A. Khokhar, Leah H. Jamie...
ISSS
1996
IEEE
114views Hardware» more  ISSS 1996»
15 years 11 months ago
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
In this paper we present the problem of flow graph balancing for minimizingthe required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cy...
Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, ...
OGAI
1993
15 years 11 months ago
Combining Neural Networks and Fuzzy Controllers
Fuzzy controllers are designed to work with knowledge in the form of linguistic control rules. But the translation of these linguistic rules into the framework of fuzzy set theory ...
Detlef Nauck, Frank Klawonn, Rudolf Kruse
ARITH
2007
IEEE
15 years 10 months ago
Robust Energy-Efficient Adder Topologies
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determi...
Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, R...