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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 24 days ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
IWCMC
2006
ACM
16 years 23 days ago
Optimal hierarchical energy efficient design for MANETs
Due to the growing interest in mobile wireless Ad-Hoc networks’ (MANETs) applications, researchers have proposed many routing protocols that differ in their objective. Energy ef...
Wasim El-Hajj, Dionysios Kountanis, Ala I. Al-Fuqa...
DAC
2005
ACM
16 years 7 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
DCOSS
2005
Springer
16 years 10 days ago
Design of Adaptive Overlays for Multi-scale Communication in Sensor Networks
In wireless sensor networks, energy and communication bandwidth are precious resources. Traditionally, layering has been used as a design principle for network stacks; hence routin...
Santashil PalChaudhuri, Rajnish Kumar, Richard G. ...
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
15 years 11 months ago
Memory System Connectivity Exploration
In programmable embedded systems, the memory subsystem represents a major cost, performance and power bottleneck. To optimize the system for such different goals, the designer wou...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau