3120 search results - page 302 / 624 » An optimal architecture for a DDC |
183
Voted
DAC
2005
ACM
16 years 7 months ago
2005
ACM
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
206
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VLSID
2007
IEEE
16 years 7 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
189
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HPCA
2002
IEEE
16 years 7 months ago
2002
IEEE
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
180
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ICRA
2008
IEEE
16 years 1 months ago
2008
IEEE
— In this work, we have extended the concept of constrained motion control of robots to surgical tasks that require multiple robots. We present virtual fixtures to guide the mot...
294
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HPCA
2007
IEEE
16 years 1 months ago
2007
IEEE
Shared memory multiprocessors play an increasingly important role in enterprise and scientific computing facilities. Remote misses limit the performance of shared memory applicat...