3120 search results - page 289 / 624 » An optimal architecture for a DDC |
181
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DAC
2011
ACM
14 years 6 months ago
2011
ACM
We present ChronOS Linux, a best-effort real-time Linux kernel for chip multiprocessors (CMPs). ChronOS addresses the intersection of three problem spaces: a) OS-support for obta...
259
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ARC
2012
Springer
14 years 2 months ago
2012
Springer
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
152
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CAV
2012
Springer
13 years 9 months ago
2012
Springer
The growing complexity of hardware optimizations employed by multiprocessors leads to subtle distinctions among allowed and disallowed behaviors, posing challenges in specifying th...
184
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DAC
2012
ACM
13 years 9 months ago
2012
ACM
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
425
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DAC
2012
ACM
13 years 9 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...