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» An optimal architecture for a DDC
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150
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VLSID
2002
IEEE
109views VLSI» more  VLSID 2002»
16 years 7 months ago
Probabilistic Analysis of Rectilinear Steiner Trees
Steiner tree is a fundamental problem in the automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner t...
Chunhong Chen
MICRO
2009
IEEE
137views Hardware» more  MICRO 2009»
16 years 1 months ago
ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem
Dynamic Random Access Memory (DRAM) is used as the bulk of the main memory in most computing systems and its energy and power consumption has become a first-class design considera...
Ciji Isen, Lizy Kurian John
MICRO
2006
IEEE
73views Hardware» more  MICRO 2006»
16 years 22 days ago
Merging Head and Tail Duplication for Convergent Hyperblock Formation
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
Bertrand A. Maher, Aaron Smith, Doug Burger, Kathr...
CODES
2002
IEEE
15 years 11 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
160
Voted
GECCO
2010
Springer
158views Optimization» more  GECCO 2010»
15 years 11 months ago
A genetic algorithm to improve linux kernel performance on resource-constrained devices
As computers become increasingly mobile, users demand more functionality, longer battery-life, and better performance from mobile devices. In response, chipset fabricators are foc...
James Kukunas, Robert D. Cupper, Gregory M. Kapfha...