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» An optimal architecture for a DDC
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IPPS
2003
IEEE
15 years 12 months ago
ECO: An Empirical-Based Compilation and Optimization System
In this paper, we describe a compilation system that automates much of the process of performance tuning that is currently done manually by application programmers interested in h...
Nastaran Baradaran, Jacqueline Chame, Chun Chen, P...
SBACPAD
2003
IEEE
103views Hardware» more  SBACPAD 2003»
15 years 12 months ago
Profiling and Optimization of Software-Based Network-Analysis Applications
A large set of tools for network monitoring and accounting, security, traffic analysis and prediction — more broadly, for network operation and management — require direct and...
Loris Degioanni, Mario Baldi, Fulvio Risso, Gianlu...
OTM
2009
Springer
15 years 11 months ago
Optimizing Data Management in Grid Environments
Grids currently serve as platforms for numerous scientific as well as business applications that generate and access vast amounts of data. In this paper, we address the need for e...
Antonis Zissimos, Katerina Doka, Antony Chazapis, ...
ICCD
2002
IEEE
114views Hardware» more  ICCD 2002»
16 years 3 months ago
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Che...
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
16 years 1 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh