3120 search results - page 269 / 624 » An optimal architecture for a DDC |
168
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ASPDAC
2009
ACM
16 years 1 months ago
2009
ACM
The Leading Zero Anticipator (LZA) is one of the main components used in floating point addition. It tends to be on the critical path, so it has attracted the attention of many r...
155
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INFOCOM
2007
IEEE
16 years 1 months ago
2007
IEEE
—In the past years, electronic routers have had trouble keeping up with the increase in optical fiber capacity. As their power consumption has grown exponentially and already ex...
205
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HIPC
2007
Springer
16 years 26 days ago
2007
Springer
: The Cell is a heterogeneous multi-core processor, which has eight co-processors, called SPEs. The SPEs can access a common shared main memory through DMA, and each SPE can direct...
178
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APCSAC
2006
IEEE
16 years 23 days ago
2006
IEEE
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the perform...
196
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IPPS
2006
IEEE
16 years 22 days ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...