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» An optimal architecture for a DDC
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CODES
2008
IEEE
16 years 1 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
16 years 28 days ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
MIDDLEWARE
2007
Springer
16 years 23 days ago
A Utility-Aware Middleware Architecture for Decentralized Group Communication Applications
Abstract. The success of Internet telephony services like Skype illustrates the feasibility of utilizing unstructured Peer-to-Peer (P2P) networks as an economical platform for supp...
Jianjun Zhang, Ling Liu, Lakshmish Ramaswamy, Gong...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
16 years 1 days ago
Divide and concatenate: a scalable hardware architecture for universal MAC
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
Bo Yang, Ramesh Karri, David A. McGrew
SAC
2003
ACM
15 years 12 months ago
Systems Architecture for Pervasive Retail
Recent developments in mobile technologies and associated economies of scale via mature manufacturing processes have made possible the construction of pervasive systems in specifi...
George Roussos, Panos Kourouthanasis, Eugene A. Gr...