3120 search results - page 241 / 624 » An optimal architecture for a DDC |
183
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ISCA
2008
IEEE
16 years 1 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
175
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ICPPW
2005
IEEE
16 years 7 days ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
161
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
176
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SOSP
2009
ACM
16 years 3 months ago
2009
ACM
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
191
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PPOPP
2010
ACM
16 years 1 months ago
2010
ACM
This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information ...