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» An optimal architecture for a DDC
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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 11 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
ICCAD
2006
IEEE
96views Hardware» more  ICCAD 2006»
16 years 3 months ago
Loop pipelining for high-throughput stream computation using self-timed rings
We present a technique for increasing the throughput of stream processing architectures by removing the bottlenecks caused by loop structures. We implement loops as self-timed pip...
Gennette Gill, John Hansen, Montek Singh
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
16 years 21 days ago
Top-down heterogeneous synthesis of analog and mixed-signal systems
A new approach for automated synthesis of analog and mixed-signal systems is presented. The heterogeneous genetic optimization strategy starts from a functional description and ev...
Ewout Martens, Georges G. E. Gielen
DEXAW
2006
IEEE
122views Database» more  DEXAW 2006»
16 years 21 days ago
Agent-Based Petroleum Offshore Monitoring Using Sensor Networks
This paper investigates the architecture and design of agent-based sensor networks for petroleum offshore monitoring. A few challenges to monitor the reservoir, wellbore and wellh...
Sajid Hussain, Md. Rafiqul Islam, Elhadi Shakshuki...
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
16 years 7 days ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...