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» An optimal architecture for a DDC
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CODES
2003
IEEE
15 years 12 months ago
A multiobjective optimization model for exploring multiprocessor mappings of process networks
In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes se...
Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel
SIGMOD
2007
ACM
136views Database» more  SIGMOD 2007»
16 years 6 months ago
Progressive optimization in a shared-nothing parallel database
Commercial enterprise data warehouses are typically implemented on parallel databases due to the inherent scalability and performance limitation of a serial architecture. Queries ...
Wook-Shin Han, Jack Ng, Volker Markl, Holger Kache...
CODES
2005
IEEE
16 years 7 days ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
DAC
2009
ACM
16 years 1 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
ARC
2009
Springer
165views Hardware» more  ARC 2009»
16 years 1 months ago
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
Xu Guo, Patrick Schaumont