3120 search results - page 231 / 624 » An optimal architecture for a DDC |
201
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ICMCS
2008
IEEE
16 years 1 months ago
2008
IEEE
The efficient implementation of multimedia algorithms, for the ever increasing complexity of the specifications and the emergence of the new generation of processing platforms c...
205
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ARC
2007
Springer
16 years 24 days ago
2007
Springer
Abstract. The novel design of high-speed and low-energy FPGA routing architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced. For that purpose,...
172
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HPCA
2003
IEEE
16 years 7 months ago
2003
IEEE
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...
198
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IPPS
1999
IEEE
15 years 11 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
210
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DAC
2010
ACM
15 years 4 months ago
2010
ACM
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlev...