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» An optimal architecture for a DDC
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DAC
2000
ACM
16 years 7 months ago
Performance analysis and optimization of latency insensitive systems
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
VLSID
2004
IEEE
112views VLSI» more  VLSID 2004»
16 years 7 months ago
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization
It has been observed that even highly optimized software programs perform "redundant" computations during their execution, due to the nature (statistics) of the values a...
Weidong Wang, Anand Raghunathan, Niraj K. Jha
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
16 years 1 months ago
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
Saraju P. Mohanty
DOCENG
2004
ACM
16 years 1 days ago
Logic-based XPath optimization
XPath [16] was introduced by the W3C as a standard language for specifying node selection, matching conditions, and for computing values from an XML document. XPath is now used in...
Pierre Genevès, Jean-Yves Vion-Dury
SSPR
2004
Springer
15 years 12 months ago
Feature Subset Selection Using an Optimized Hill Climbing Algorithm for Handwritten Character Recognition
This paper presents an optimized Hill Climbing algorithm to select a subset of features for handwritten character recognition. The search is conducted taking into account a random ...
Carlos M. Nunes, Alceu de Souza Britto Jr., Celso ...