3120 search results - page 214 / 624 » An optimal architecture for a DDC |
172
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ISLPED
2005
ACM
16 years 5 days ago
2005
ACM
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
194
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GCC
2005
Springer
16 years 3 days ago
2005
Springer
Spatial Information Grid (SIG) is a project of applying grid technology to share and integrate spatial data resources, information processing resources, equipment resources, and kn...
172
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ICS
2005
Tsinghua U.
16 years 3 days ago
2005
Tsinghua U.
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
172
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CF
2004
ACM
16 years 1 days ago
2004
ACM
Nanoelectronics research has primarily focused on devices. By contrast, not much has been published on innovations at higher layers: we know little about how to construct circuits...
199
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WMPI
2004
ACM
16 years 16 hour ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...