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» An optimal architecture for a DDC
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DATE
2007
IEEE
114views Hardware» more  DATE 2007»
16 years 28 days ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
IPPS
2007
IEEE
16 years 27 days ago
Advanced Shortest Paths Algorithms on a Massively-Multithreaded Architecture
We present a study of multithreaded implementations of Thorup’s algorithm for solving the Single Source Shortest Path (SSSP) problem for undirected graphs. Our implementations l...
Joseph R. Crobak, Jonathan W. Berry, Kamesh Maddur...
ISMAR
2007
IEEE
16 years 26 days ago
A System Architecture for Ubiquitous Tracking Environments
Ubiquitous tracking setups, covering large tracking areas with many heterogeneous sensors of varying accuracy, require dedicated middleware to facilitate development of stationary...
Manuel Huber, Daniel Pustka, Peter Keitler, Floria...
SBACPAD
2007
IEEE
110views Hardware» more  SBACPAD 2007»
16 years 26 days ago
Architectural Breakdown of End-to-End Latency in a TCP/IP Network
Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-e...
Steen Larsen, Parthasarathy Sarangam, Ram Huggahal...
CC
2007
Springer
126views System Software» more  CC 2007»
16 years 23 days ago
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
K. Shyam, R. Govindarajan