3120 search results - page 210 / 624 » An optimal architecture for a DDC |
175
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ICCAD
2005
IEEE
16 years 6 days ago
2005
IEEE
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
168
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APCSAC
2003
IEEE
15 years 12 months ago
2003
IEEE
Static nodes, e.g. houses, educational institutions etc, can comprise ad-hoc networks using off-the-self wireless technologies with a view to bypass expensive telecommunication so...
174
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IEEEPACT
2003
IEEE
15 years 12 months ago
2003
IEEE
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...
190
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
188
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MICRO
2002
IEEE
15 years 11 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...