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» An optimal architecture for a DDC
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DATE
2008
IEEE
107views Hardware» more  DATE 2008»
16 years 1 months ago
Instruction Set Extension Exploration in Multiple-Issue Architecture
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized ins...
I-Wei Wu, Zhi-Yuan Chen, Jean Jyh-Jiun Shann, Chun...
GLOBECOM
2007
IEEE
16 years 28 days ago
Virtualization of Local Computer Bus Architectures Over the Internet
We propose a companion solution to iSCSI that is more suited for virtualization of local computer bus architectures, such as PCI/PCI-X and PCI Express. We explore the architecture ...
David A. Daniel, Joseph Y. Hui
IPPS
2007
IEEE
16 years 27 days ago
Reconfigurable Architecture for Biological Sequence Comparison in Reduced Memory Space
DNA sequence alignment is a very important problem in bioinformatics. The algorithm proposed by Smith-Waterman (SW) is an exact method that obtains optimal local alignments in qua...
Azzedine Boukerche, Jan Mendonca Correa, Alba Cris...
ISCA
2005
IEEE
147views Hardware» more  ISCA 2005»
16 years 5 days ago
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 12 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...