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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
15 years 12 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 12 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
15 years 11 months ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
WWW
2004
ACM
16 years 7 months ago
Cooperative middleware specialization for service oriented architectures
Service-oriented architectures (SOA) will provide the basis of the next generation of distributed software systems, and have already gained enormous traction in the industry throu...
Nirmal Mukhi, Ravi B. Konuru, Francisco Curbera
HPCA
2009
IEEE
16 years 7 months ago
Eliminating microarchitectural dependency from Architectural Vulnerability
The Architectural Vulnerability Factor (AVF) of a hardware structure is the probability that a fault in the structure will affect the output of a program. AVF captures both microa...
Vilas Sridharan, David R. Kaeli