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» An optimal architecture for a DDC
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DATE
1997
IEEE
95views Hardware» more  DATE 1997»
15 years 10 months ago
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...
Patrick Schaumont, Serge Vernalde, Luc Rijnders, M...
ASPDAC
2007
ACM
115views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Model-based Programming Environment of Embedded Software for MPSoC
- A noble model-based programming environment of embedded software for MPSoC is proposed. By defining a common intermediate code (CIC), it separates modeling of the software and im...
Soonhoi Ha
ARC
2006
Springer
135views Hardware» more  ARC 2006»
15 years 10 months ago
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection
To fill the gap between increasing demand for reconfigurability and performance efficiency, CGRAs are seen to be an emerging platform. In this paper, a new architecture, QUKU, is d...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker
ASAP
1995
IEEE
145views Hardware» more  ASAP 1995»
15 years 10 months ago
An array processor for inner product computations using a Fermat number ALU
This paper explores an architecture for parallel independent computations of inner products over the direct product ring . The structure is based on the polynomial mapping of the ...
Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, Wil...
ASPDAC
2008
ACM
116views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Faster projection based methods for circuit level verification
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates the verification of digital circuits us...
Chao Yan, Mark R. Greenstreet