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» An optimal architecture for a DDC
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FCCM
2004
IEEE
133views VLSI» more  FCCM 2004»
15 years 10 months ago
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
Intrusion detection for network security is a computation intensive application demanding high system performance. System level design, a relatively unexplored field in this area,...
Zachary K. Baker, Viktor K. Prasanna
ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
15 years 10 months ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...
CVPR
2010
IEEE
15 years 9 months ago
Robust Piecewise-Planar 3D Reconstruction and Completion from Large-Scale Unstructured Point Data
In this paper, we present a novel method, the first to date to our knowledge, which is capable of directly and automatically producing a concise and idealized 3D representation f...
Anne-Laure Chauve, Patrick Labatut, Jean-Philippe ...
ARC
2008
Springer
126views Hardware» more  ARC 2008»
15 years 8 months ago
DNA Physical Mapping on a Reconfigurable Platform
Reconfigurable architectures enable the hardware function to be implemented by the user and, due to its characteristics, have been used in many areas, including Bioinformatics. One...
Adriano Idalgo, Nahri Moreano
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
15 years 8 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy