3120 search results - page 193 / 624 » An optimal architecture for a DDC |
166
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CHES
2006
Springer
15 years 10 months ago
2006
Springer
A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve,...
193
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CASES
2008
ACM
15 years 8 months ago
2008
ACM
Various commercial programmable compute platforms have their processor architecture enhanced with field-programmable gate arrays (FPGAs). In a common usage scenario, an applicatio...
163
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
We propose a hierarchical mixed signal design methodology based on the principles of Platform-Based Design (PBD). The methodology is a meet-in-the-middle approach where design com...
191
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem ext...
166
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...