3120 search results - page 191 / 624 » An optimal architecture for a DDC |
169
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
179
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ISCA
2005
IEEE
16 years 4 days ago
2005
IEEE
Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network, and at the heart of alm...
173
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CAEPIA
2005
Springer
16 years 3 days ago
2005
Springer
This paper presents an architecture that makes it possible to construct dynamic systems capable of growing in dimension and adapting its knowledge to environmental changes. An arch...
153
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ICMCS
2005
IEEE
16 years 4 days ago
2005
IEEE
This paper presents the optimization techniques and results of implementing the H.264/AVC baseline profile decoder in software on the Sandblaster digital signal processor. It has ...
188
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DAC
1997
ACM
15 years 10 months ago
1997
ACM
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken [14] proposed an optimal dynamic programming solution (with extensions propose...