3120 search results - page 180 / 624 » An optimal architecture for a DDC |
176
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MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
169
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ICS
2010
Tsinghua U.
15 years 11 months ago
2010
Tsinghua U.
We explore the intersection between an emerging class of architectures and a prominent workload: GPGPUs (General-Purpose Graphics Processing Units) and regular expression matching...
161
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DAC
1999
ACM
15 years 11 months ago
1999
ACM
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed ...
193
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DAC
2010
ACM
15 years 4 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
156
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CEC
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract— The role of gradient estimation in global optimization is investigated. The concept of a regional gradient is introduced as a tool for analyzing and comparing different...