3120 search results - page 156 / 624 » An optimal architecture for a DDC |
197
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CODES
2006
IEEE
16 years 17 days ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
196
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DEXAW
2006
IEEE
16 years 17 days ago
2006
IEEE
One of the pre-requisites for the realization of the Semantic Web vision are matching techniques which are capable of handling the open, dynamic and heterogeneous nature of the se...
189
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PCI
2005
Springer
15 years 12 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
178
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
177
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GLVLSI
2000
IEEE
15 years 11 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...