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DFT
2003
IEEE
64views VLSI» more  DFT 2003»
15 years 11 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
IEEEPACT
2002
IEEE
15 years 11 months ago
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
Jaewook Shin, Jacqueline Chame, Mary W. Hall
TVLSI
2002
102views more  TVLSI 2002»
15 years 6 months ago
Low-power data forwarding for VLIW embedded architectures
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
ICALT
2007
IEEE
16 years 25 days ago
Embracing Cognitive Aspects in Web Personalization Environments -- The AdaptiveWeb Architecture
This paper1 presents a Web adaptation and personalization architecture that uses cognitive aspects as its core filtering element. The innovation of the proposed architecture focus...
Panagiotis Germanakos, Nikos Tsianos, Zacharias Le...
TRUSTBUS
2010
Springer
15 years 4 months ago
A Privacy-Preserving Architecture for the Semantic Web Based on Tag Suppression
We propose an architecture that preserves user privacy in the semantic Web via tag suppression. In tag suppression, users may wish to tag some resources and refrain from tagging so...
Javier Parra-Arnau, David Rebollo-Monedero, Jordi ...