3120 search results - page 153 / 624 » An optimal architecture for a DDC |
187
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
154
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NIPS
2007
15 years 8 months ago
2007
The classical hypothesis, that bottom-up saliency is a center-surround process, is combined with a more recent hypothesis that all saliency decisions are optimal in a decision-the...
182
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IPPS
2007
IEEE
16 years 24 days ago
2007
IEEE
1 Multi-paradigm, multi-threaded and multi-core computing devices available today provide several orders of magnitude performance improvement over mainstream microprocessors. These...
167
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DATE
2005
IEEE
16 years 3 days ago
2005
IEEE
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
178
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ISCAS
2005
IEEE
16 years 2 days ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...