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» An optimal architecture for a DDC
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LCPC
2004
Springer
15 years 12 months ago
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism
Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor a...
Lakshmi N. Chakrapani, John C. Gyllenhaal, Wen-mei...
BIBE
2008
IEEE
142views Bioinformatics» more  BIBE 2008»
16 years 29 days ago
Optimizing performance, cost, and sensitivity in pairwise sequence search on a cluster of PlayStations
— The Smith-Waterman algorithm is a dynamic programming method for determining optimal local alignments between nucleotide or protein sequences. However, it suffers from quadrati...
Ashwin M. Aji, Wu-chun Feng
DAC
2006
ACM
16 years 13 days ago
Use of C/C++ models for architecture exploration and verification of DSPs
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
David Brier, Raj S. Mitra
IPSN
2005
Springer
15 years 12 months ago
A robust architecture for distributed inference in sensor networks
— Many inference problems that arise in sensor networks require the computation of a global conclusion that is consistent with local information known to each node. A large class...
Mark A. Paskin, Carlos Guestrin, Jim McFadden
VLSID
2002
IEEE
78views VLSI» more  VLSID 2002»
16 years 6 months ago
Optimization of Test Accesses with a Combined BIST and External Test Scheme
External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architectu...
Makoto Sugihara, Hiroto Yasuura