3120 search results - page 145 / 624 » An optimal architecture for a DDC |
173
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INFOCOM
2007
IEEE
16 years 23 days ago
2007
IEEE
— The Valiant Load-Balancing (VLB) design has been proposed for a backbone network architecture that can efficiently provide predictable performance under changing traffic matr...
124
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
170
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DATE
2007
IEEE
16 years 24 days ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
137
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ATAL
2004
Springer
15 years 12 months ago
2004
Springer
Abstract. Companies in today’s automotive industry are under immense competitive pressure to reduce the length of their product development cycle from initial concept to begin of...
160
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APLAS
2003
ACM
15 years 11 months ago
2003
ACM
This paper studies the problem of resource availability in the context of mobile code for embedded systems such as smart cards. It presents an architecture dedicated to controlling...