3120 search results - page 142 / 624 » An optimal architecture for a DDC |
162
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
160
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IEEEPACT
2003
IEEE
15 years 11 months ago
2003
IEEE
Effective modeling and management of hardware resources have always been critical toward generating highly efficient code in static compilers. With Just-In-Time compilation and dy...
188
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DATE
2007
IEEE
16 years 24 days ago
2007
IEEE
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
148
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DATE
2006
IEEE
16 years 16 days ago
2006
IEEE
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
147
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ISCA
2005
IEEE
16 years 1 days ago
2005
IEEE
Sensor network processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performa...